Adaptec AIC-6915 Technical Information

Document Title: ABA-1030 DVB Satellite ReceiverStock Number: 512130-00, Rev. A Cover-1Print Spec Number: 497767-00, Rev. AACurrent Date: 10/10/98Progr

Document Title: Document TitleStock Number: xxxxxx-xx Rev. x Page: Front Matter-viiiPrint Spec Number: xxxxxx-xx Rev. xCurrent Date: 10/10/98 ECN Date

7-28 AIC-6915 Ethernet LAN Controller Programmer’s ManualTimersControl RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByt

7-29Register Descriptions12 r/w 0RxHiPrBypass: If this bit is set, bypass the interrupt masking timer when generating RxDoneInt after DMA-transferring

7-30 AIC-6915 Ethernet LAN Controller Programmer’s ManualThe following interrupts are affected by the masking time: RxQ1DoneInt EarlyRxQ1Int RxQ2DoneI

7-31Register DescriptionsInterruptStatus RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: 80h - 83hThis reg

7-32 AIC-6915 Ethernet LAN Controller Programmer’s Manual19 r/w 0DmaErrInt: This bit is set on a DMA error. The DMA errors are: Target abort, Master a

7-33Register Descriptions10 r/w 0EarlyRxQ1Int: This bit is set after the DMA transfer of a programmable number of bytes of a received frame. The progr

7-34 AIC-6915 Ethernet LAN Controller Programmer’s ManualShadowInterruptStatus RegisterType: RInternal Registers Subgroup: Ethernet Functional Registe

7-35Register DescriptionsInterruptEn RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: 88h - 8BhSpecifies if

7-36 AIC-6915 Ethernet LAN Controller Programmer’s ManualGPIO RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address

7-37Register DescriptionsTransmit RegistersTxDescQueueCtrl RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address:

ixDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx Rev. x Page: Front Matter-ixPrint Spec Number: xxxxxx-x

7-38 AIC-6915 Ethernet LAN Controller Programmer’s ManualNote: Maximum transmit descriptor queue length 16-KBytes for the high-priority queue and 16-K

7-39Register DescriptionsHiPrTxDescQueueBaseAddr RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: 94h - 97h

7-40 AIC-6915 Ethernet LAN Controller Programmer’s ManualTxDescQueueHighAddr RegisterType: R/W Internal Registers Subgroup: Ethernet Functional Regist

7-41Register DescriptionsTxDescQueueConsumerIndex RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: A4h- A7h T

7-42 AIC-6915 Ethernet LAN Controller Programmer’s ManualTxDmaStatus2Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address:

7-43Register DescriptionsCompletion Queue RegistersNote: All completion queues have a fixed size of 1KByte entries.CompletionQueueHighAddr RegisterTyp

7-44 AIC-6915 Ethernet LAN Controller Programmer’s ManualRxCompletionQueue1CtrlType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByt

7-45Register DescriptionsRxCompletionQueue2CtrlType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: C0h - C3h 3:0 r/w 0

7-46 AIC-6915 Ethernet LAN Controller Programmer’s ManualCompletionQueueConsumerIndexType: R/W Internal Registers Subgroup: Ethernet Functional Regist

7-47Register DescriptionsCompletionQueueProducerIndexType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: C8h - CBhRxHi

x AIC-6915 Ethernet LAN Controller Programmer’s ManualDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx Rev

7-48 AIC-6915 Ethernet LAN Controller Programmer’s ManualReceive RegistersRxDmaCtrlType: R/W Internal Registers Subgroup: Ethernet Functional Register

7-49Register Descriptions22:20 r/w 0RxDmaQueueMode[2:0]: This field determines how to select the DMA buffer descriptor queue. The encoding is as follo

7-50 AIC-6915 Ethernet LAN Controller Programmer’s ManualRxDescQueue1CtrlType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Addr

7-51Register Descriptions13 r/w 0RxVariableSizeQueues: Indicates the Rx descriptor mode:‘0’ - Fixed size queue is used.‘1’ - Variable size queue is us

7-52 AIC-6915 Ethernet LAN Controller Programmer’s ManualRxDescQueue2CtrlType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Addr

7-53Register DescriptionsRxDescQueue2LowAddressType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Address: E4h - E7h RxDescQueue

7-54 AIC-6915 Ethernet LAN Controller Programmer’s ManualRxDescQueue2PtrsType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Addr

7-55Register DescriptionsRxAddressFilteringCtrl RegisterAddress filtering, which is controlled by the RXADDRESSFILTERINGCTRL register and various addr

7-56 AIC-6915 Ethernet LAN Controller Programmer’s ManualTable 7-71. RxAddressFilteringCtrl Register Bit(s) rwReset Value Description/Function31:16 r/

7-57Register Descriptions7:6 r/w 0PerfectFilteringMode[1:0] ‘00’ - Perfect filtering disabled. ‘01’ - 16 perfect addresses filtering. The AIC-6915 com

xiTablesDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx Rev. x Page: Front Matter-xiPrint Spec Number: xx

7-58 AIC-6915 Ethernet LAN Controller Programmer’s ManualRxFrameTestOut RegisterType: R Internal Registers Subgroup: Ethernet Functional RegistersByte

7-59Register DescriptionsPCI Diagnostic RegistersThe following registers are accessible from PCI configuration, memory, and indirect I/O space. They a

7-60 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCIMasterStatus1 RegisterType: RInternal Registers Subgroup: PCI Extra RegistersByte Address:

7-61Register DescriptionsPCIMasterStatus2 RegisterType: RInternal Registers Subgroup: PCI Extra RegistersByte Address: 0108h-010Bh PCIDmaLowHostAddr R

7-62 AIC-6915 Ethernet LAN Controller Programmer’s ManualBacDmaDiagnostic0 RegisterType: RInternal Registers Subgroup: PCI Extra RegistersByte Address

7-63Register DescriptionsBacDmaDiagnostic2 RegisterType: RInternal Registers Subgroup: PCI Extra RegistersByte Address: 0118h - 011BhThis register p

7-64 AIC-6915 Ethernet LAN Controller Programmer’s ManualBacDmaDiagnostic3 RegisterType: RInternal Registers Subgroup: PCI Functional RegistersByte Ad

7-65Register DescriptionsMacAddr1 RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersByte Address: 0120h - 0123hNIC’s MAC Addr Byte

7-66 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI CardBus RegistersThe following registers are defined in the CardBus PC Card Electrical Sp

7-67Register DescriptionsFunctionEventMask RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersByte Address: 0134h - 0137hControls w

xii AIC-6915 Ethernet LAN Controller Programmer’s ManualDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx R

7-68 AIC-6915 Ethernet LAN Controller Programmer’s ManualForceFunction RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersByte Addr

7-69Register DescriptionsAdditional Ethernet RegistersThe following group of registers control access to the MAC, physical device (MII), transmit FP,

7-70 AIC-6915 Ethernet LAN Controller Programmer’s ManualTestMode Register (TBD)Type: R/W Internal Registers Subgroup: Ethernet Extra RegistersByte Ad

7-71Register DescriptionsMAC Control RegistersMacConfig1 RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5000h - 5003hTabl

7-72 AIC-6915 Ethernet LAN Controller Programmer’s ManualFor proper operation, the internal MAC must be reset after enabling any of the configuration

7-73Register DescriptionsMacConfig2 RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5004h- 5007h Table 7-92. MacConfig2 Re

7-74 AIC-6915 Ethernet LAN Controller Programmer’s ManualFor proper operation, the internal MAC must be reset after enabling any of the configuration

7-75Register DescriptionsNonBkToBkIPG RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 500Ch- 500Fh ColRetry RegisterType:

7-76 AIC-6915 Ethernet LAN Controller Programmer’s ManualMaxLength RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5014h -

7-77Register DescriptionsReTxCnt RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5020h- 5023h RandomNumGen RegisterType: R

1-11▼▼▼▼Introduction The Adaptec AIC-6915, PCI 10/100 Ethernet LAN Controller provides advanced Ethernet adapter features in a single chip optimized f

7-78 AIC-6915 Ethernet LAN Controller Programmer’s ManualMskRandomNum RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5028

7-79Register DescriptionsRxByteCnt RegisterType: R/W Internal Registers Subgroup: MAC RegistersByte Address: 5040h- 5043h TxPauseTimer RegisterType:

7-80 AIC-6915 Ethernet LAN Controller Programmer’s ManualMIIStatus RegisterType: R/WInternal Registers Subgroup: MAC RegistersByte Address: 5070h -

7-81Register DescriptionsSince each external PHY takes up 128 bytes (32 x 32 bits), the actual address offset to access each of them through the AIC-6

7-82 AIC-6915 Ethernet LAN Controller Programmer’s ManualAddress Filtering RegistersPerfect Address Memory RegisterType: R/WInternal Registers Subgrou

7-83Register DescriptionsPerfect AddressesThe AIC-6915 compares the destination address of the incoming frame against all of the perfect addresses sto

7-84 AIC-6915 Ethernet LAN Controller Programmer’s ManualMAC Statistic RegistersType: R/WInternal Registers Subgroup: MAC Statistic Byte Address: 70

7-85Register Descriptions34h Frames Lost due to Internal Transmit Errors. (Cannot recover from FIFO underrun)TX R 32 Count the number of frames which

7-86 AIC-6915 Ethernet LAN Controller Programmer’s ManualNote: Due to the limitation of the SRAM size, Receive Multicast, Broadcast, and VLAN packets

7-87Register DescriptionsTransmit Frame Processor - TxGfpMemType: R/W Internal Registers Subgroup: Transmit Frame Processor RegisterByte Address: 80

1-2 AIC-6915 Ethernet LAN Controller Programmer’s ManualFeaturesGeneral Supports four general purpose I/Os that can be programmed separately as inputs

8-18▼▼▼▼Sample DriverThe following sample driver documentation is intended as a guide for the software developer writing a device driver for the Adapt

8-2 AIC-6915 Ethernet LAN Controller Programmer’s ManualProducer-Consumer Model for the AIC-6915The AIC-6915 uses the Producer-Consumer model for its

8-3Sample DriverBasic Register Initialization and Reset SequenceThe first step in the initialization process is NIC recognition. The most straightfor

8-4 AIC-6915 Ethernet LAN Controller Programmer’s Manual1PCI COMMAND Register (offset 04h): The PCI Command register must be initialized to enable mem

8-5Sample Driver8InterruptStatus (offset 80h): The InterruptStatus register should be set to zero during initialization. There are two types of statu

8-6 AIC-6915 Ethernet LAN Controller Programmer’s Manual// Other fields in MacConfig1 may remain at the default valueAIC6915_WRITE_REG(Adapter->Reg

8-7Sample Driver// Specify which interrupts we wantInterruptEnValue.RxQ1DoneIntEn = 1;// interrupt on receive DMAInterruptEnValue.TxDmaDoneIntEn = 1;/

8-8 AIC-6915 Ethernet LAN Controller Programmer’s ManualType 2 Completion Descriptor The Type 2 descriptor is also known as the checksum completion de

8-9Sample DriverTwo Receive QueuesThe AIC-6915 offers the ability to use two Receive Completion Descriptors Queues and two Receive Buffer Descriptor Q

1-3Introduction Supports 32- and 64-bit addressing of Host DMA buffers and DMA descriptor queues Big/Little endian support for data and descriptors Sp

8-10 AIC-6915 Ethernet LAN Controller Programmer’s Manual1RXCOMPLETIONQUEUE1CTRL (offset BCh): This register is used to define the location and type

8-11Sample Driver6RXDMACTRL (offset D0h): This register controls receive DMA operation and frame acceptance criteria. Required Fields:– RxCompletionQ

8-12 AIC-6915 Ethernet LAN Controller Programmer’s Manual11RXDESCQUEUE1PTRS (offset E8h): This register contains the consumer and producer indices fo

8-13Sample Driver// assign the base address of the completion queue (high 24 bits)RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGet

8-14 AIC-6915 Ethernet LAN Controller Programmer’s Manual// If single queue, use the first queue only// Initialize RxDescQueue1LowAddress// Allocate m

8-15Sample DriverReceive Interrupt HandlingWhen a packet is received, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue and gen

8-16 AIC-6915 Ethernet LAN Controller Programmer’s Manual// RxBufferRing structure contains pointers to physical and virtual// buffer addresses, and f

8-17Sample Drivertransmit completion interrupt which is enabled. The Transmit Completion Descriptors are described in more detail below.Transmit Comp

8-18 AIC-6915 Ethernet LAN Controller Programmer’s Manualof descriptor. These descriptors are outlined below. For a complete description, refer to t

8-19Sample DriverTransmit Producer or Consumer index to a software array index. The size of a Type 1 descriptor in bytes is calculated using the form

1-4 AIC-6915 Ethernet LAN Controller Programmer’s Manual– Memory Write And Invalidate Supports PCI bus address and data parity generation and checkin

8-20 AIC-6915 Ethernet LAN Controller Programmer’s ManualTo convert the hardware Transmit Producer or Consumer index to a software index, multiply the

8-21Sample DriverTransmit InitializationThe AIC-6915 provides a set of registers which must be initialized in preparation for transmitting packets. T

8-22 AIC-6915 Ethernet LAN Controller Programmer’s Manual5TXDESCQUEUEPRODUCERINDEX (offset A0h): This register contains the producer index for both t

8-23Sample DriverRequired Fields:– RxCompletionQ1ConsumerIndex = 0: Initialize the Receive Completion Descriptor Queue 1 consumer index to zero. Note

8-24 AIC-6915 Ethernet LAN Controller Programmer’s Manual// Set up the low 32 bits of the low priority transmit descriptor queue// base addressLoPrTxD

8-25Sample DriverTransmit HandlingIn the code fragment below, the operating system has called the transmit routine with a packet to be transmitted. T

8-26 AIC-6915 Ethernet LAN Controller Programmer’s ManualAdapter->MapRegisterIndex,TRUE,PhysicalSegmentArray,&BufferPhysicalSegments);// Put ea

8-27Sample Driver&CurrentBuffer);} // while (CurrentBuffer)// We’ve placed all the buffers in this packet into Transmit Buffer // Descriptors.// W

8-28 AIC-6915 Ethernet LAN Controller Programmer’s Manual// The index is a multiple of the size of the Transmit Buffer Descriptor.IndexToDescriptor =

8-29Sample DriverAIC-6915 DDK FeaturesTable 8-1 is a list of the major features available in the AIC-6915 and demonstrated in the DDK.*Additional inte

1-5IntroductionBlock DiagramFigure 1-1 is a block diagram of the AIC-6915.8 KByte SRAMCombinedTx/Rx FIFO PCIBusAccessControl SlaveAccess, system regis

8-30 AIC-6915 Ethernet LAN Controller Programmer’s ManualDDK Development EnvironmentThe drivers contained in the DDK were written for the Windows NT e

Document Title: ABA-1030 DVB Satellite ReceiverStock Number: 512130-00, Rev. A Cover-2Print Spec Number: 497767-00, Rev. AACurrent Date: 10/10/98Adapt

1-6 AIC-6915 Ethernet LAN Controller Programmer’s ManualModulesThe AIC-6915 contains the following major modules: PCI - Controls access to the PCI bus

2-12▼▼▼▼Receive ArchitectureFeaturesThe host-related Receive Architecture features are Interrupts may be delayed so that only one interrupt is generat

2-2 AIC-6915 Ethernet LAN Controller Programmer’s Manual VLAN support:– Address filtering based on VLAN– Ability to delete VLAN tag and number from fr

2-3Receive ArchitectureA programmable number of words can be skipped between buffer descriptors. This allows the driver to store data related to a buf

2-4 AIC-6915 Ethernet LAN Controller Programmer’s Manual32-bit Addressing Mode64-bit Addressing ModeDescriptor Fields: Address - The address of the bu

2-5Receive ArchitectureAccepting framesThe AIC-6915 uses two criteria when deciding whether to accept a frame: Frame address and frame quality. When r

2-6 AIC-6915 Ethernet LAN Controller Programmer’s ManualTable 2-3. Short (Type 0) Completion Entry 31 24 23

2-7Receive ArchitectureTable 2-7. Receive Completion Descriptor (Word 0)Bit(s) Description/FunctionStatus1 field29OK - The frame is good. There were n

2-8 AIC-6915 Ethernet LAN Controller Programmer’s ManualTable 2-8. Receive Completion Descriptor (Word 1)Bit(s) Description/FunctionStatus2 field31Per

2-9Receive ArchitectureThe AIC-6915 provides address filters that have an effect on which receive frames areaccepted and how they are processed. For m

Document Title: Document TitleStock Number: xxxxxx-xx Rev. x Page: Front Matter-iPrint Spec Number: xxxxxx-xx Rev. xCurrent Date: 10/10/98 ECN Date: x

3-13▼▼▼▼Transmit ArchitectureFeaturesThe main features of Transmit Architecture are Two Buffer Descriptor Queues in the Host Memory. One for high-prio

3-2 AIC-6915 Ethernet LAN Controller Programmer’s Manual There are three kinds of interrupts generated by the transmit DMA engine. A “TxDmaDoneInt” is

3-3Transmit Architecture When the amount of packet data in the FIFO exceeds the “Transmit Threshold,” or when the end of packet is already in the FIFO

3-4 AIC-6915 Ethernet LAN Controller Programmer’s ManualTransmit Data StructureFigure 3-1 illustrates the Transmit Data StructurePkt 2 Buf3CIPIBuffer

3-5Transmit ArchitectureTransmit Register Set The following is a list of transmit parameters programmed by the driver during initialization. Transmit

3-6 AIC-6915 Ethernet LAN Controller Programmer’s Manual ID: 4 bits. This field is used by the software/debugger to identify the start of a descriptor

3-7Transmit Architecture INTR: Causes setting of the interrupt status bits (TxDmaDoneInt and/or TxFrameCompleteInt) after complete transmission of the

3-8 AIC-6915 Ethernet LAN Controller Programmer’s Manual Total Packet Length: This 16-bit field defines the total packet length. If this field is zero

3-9Transmit ArchitectureType 3, 32-bit Addressing Mode (Frame Descriptor)This mode is currently not supported in the AIC-6915.Type 4, 32-bit Addressin

iiDocument Title: Document TitleStock Number: xxxxxx-xx Rev. x Page: Front Matter-iiPrint Spec Number: xxxxxx-xx Rev. xCurrent Date: 10/10/98 ECN Date

3-10 AIC-6915 Ethernet LAN Controller Programmer’s ManualTransmit Completion Queue EntryTransmit Completion Queue entries consist of two types: DMA Co

3-11Transmit ArchitectureIf the AIC-6915 is programmed to transmit two words (8 bytes), the second word (bit 63-32) is the InterruptStatus register co

4-14▼▼▼▼PCI Module ArchitectureFeatures Compliant with PCI Local Bus Specification, Revision 2.1 Compliant with Intel PCI Bus Power Management Interfa

4-2 AIC-6915 Ethernet LAN Controller Programmer’s Manual Supports PCI PERR and SERR requirements. Supports 8-bit, 256-KByte, external Memory port for

4-3PCI Module ArchitecturePCI Block DiagramFigure 4-1 is a PCI block diagram.TGTDPUTGTCTLDECODERPCI ModuleBACBus Access PCIMSTPcimaster Logic Datapath

4-4 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI Master Module The PCI master transfers data to/from system memory. Therefore, the AIC-6915

4-5PCI Module Architecture64-bit PCI Bus MasterThe AIC-6915 supports a 64-bit PCI bus master and performs 64-bit data transfers with a 64-bit target.

4-6 AIC-6915 Ethernet LAN Controller Programmer’s ManualArbitrationThe AIC-6915 drives AD[31:00] during 32-bit transfers and AD[63:0] during 64-bit tr

4-7PCI Module ArchitectureThe value of BR_A1 pin is sampled when PCI reset is active to determine if the serial EPROM data (BR_A1=1) or the default va

iiiDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx Rev. x Page: Front Matter-iiiPrint Spec Number: xxxxxx

4-8 AIC-6915 Ethernet LAN Controller Programmer’s ManualPower ManagementThe PCI bus power management defined four power states. D0 indicates the “On”

4-9PCI Module ArchitectureCardBusCardBus is the interface between a PC card and a portable device which has 32-bit busmastering capability. The CardBu

4-10 AIC-6915 Ethernet LAN Controller Programmer’s ManualTable 4-2 lists all 16 PCI commands and the corresponding AIC-6915 response. Table 4-2. Targe

4-11PCI Module ArchitectureConfiguration Address SpaceThe AIC-6915, as a single function target, supports type 0 address space accesses with a single

4-12 AIC-6915 Ethernet LAN Controller Programmer’s ManualExpansion ROM Address SpaceWhen in target mode, the AIC-6915 allows access to an 8-bit ROM/EE

4-13PCI Module ArchitecturePERR_The AIC-6915 asserts PERR_ for detected data parity errors only if PERRESPEN is asserted.As a target device, the AIC-6

4-14 AIC-6915 Ethernet LAN Controller Programmer’s ManualIllegal BehaviorAs a target, when the AIC-6915 accepts a cycle (I/O, memory, configuration) w

5-15▼▼▼▼Frame Processor ArchitectureFeatures Calculate the TCP and UDP checksum Decode frame type (TCP, UDP, ARP, RARP, IPX, Wake-up, VLAN 802.1q, Ipv

5-2 AIC-6915 Ethernet LAN Controller Programmer’s Manual LC= 0, 1 or 2, and EXCONCLOCK is set, or Read/Write instruction is executed and the Input IOR

5-3Frame Processor ArchitectureGFP Address SpaceA total of 256 address locations can be accessed by the GFP executing Read/Write instructions. The tar

iv AIC-6915 Ethernet LAN Controller Programmer’s Manual4 PCI Module ArchitectureFeatures 4-1PCI Block Diagram 4-3PCI Master Module 4-464-bit PCI Bus M

5-4 AIC-6915 Ethernet LAN Controller Programmer’s ManualExternal RegistersThe external registers are used as a standard way to communicate with other

5-5Frame Processor ArchitectureBlock DiagramFigure 5-1 is a block diagram of the Data Processing Unit.WR2[15:0]8 Input MuxBarrel ShifterWR3[15:0]Simpl

5-6 AIC-6915 Ethernet LAN Controller Programmer’s ManualInstruction FormatsTable 5-2 describes the Instruction Formats.Table 5-2. Instruction FormatsN

5-7Frame Processor ArchitectureOpcode A 3:0CheckIpv6NextHeader - Special instruction for checking the Next Header field. The GFP recognizes 8 types of

5-8 AIC-6915 Ethernet LAN Controller Programmer’s ManualOpcode E 3:0Return - Return to main program. When branching from the main program, the next in

5-9Frame Processor Architecture❒MuxSelInput1 [29:17] Controls the 8 input mux operation at ALU input 1‘0’ - Data‘1’ - WR1[15:0]‘2’ - WR2‘3’ - WR3‘4’ -

6-16▼▼▼▼AIC-6915 Internal Registers SummaryFor the following registers, the ‘Byte Address’ indicates each registers location in memory space given as

6-2 AIC-6915 Ethernet LAN Controller Programmer’s ManualAIC-6915 Functional Registers SummaryMapped to address range 0x50040-0x500FF in memory space,

6-3AIC-6915 Internal Registers Summary00B4 CompletionQueueHighAddr Completion queue control and configuration registers00B8 TxCompletionQueueCtrl00BC

v ContentsDocument Title: AIC-6915 Ethernet LAN Controller Programmer’s ManualStock Number: xxxxxx-xx Rev. x Page: Front Matter-vPrint Spec Number: x

6-4 AIC-6915 Ethernet LAN Controller Programmer’s ManualAdditional PCI Registers SummaryMapped to address range 0x50FFF-0x50100 in Memory space. These

6-5AIC-6915 Internal Registers Summary❒500C NonBkToBkIPG5010 ColRetry5014 MaxLength5018 TxNibbleCnt501C TxByteCnt5020 ReTxCnt5024 RandomNumGen5028 Msk

7-17▼▼▼▼Register DescriptionsOverviewThis section includes all the registers required for controlling, programming, and operating the AIC-6915. All re

7-2 AIC-6915 Ethernet LAN Controller Programmer’s ManualAIC-6915 Address SpaceA device on a PCI bus can be accessed using different PCI command types.

7-3Register Descriptions(E)EPROM R/W Internal registersExternal registers0x000000x40000(64KByte words (256KBytes))(~16K words (~64KBytes))(16K words (

7-4 AIC-6915 Ethernet LAN Controller Programmer’s ManualTerminologyThroughout this chapter, data values are defined as follows: Byte = 8 bits Halfword

7-5Register DescriptionsPCI RegistersPCI Configuration Header RegistersAt the deassertion edge of the PCI reset, the AIC-6915 starts reading the seria

7-6 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI Command RegisterType: R/WInternal Registers Subgroup: PCI Configuration HeaderByte Address

7-7Register DescriptionsPCI Status RegisterType: R/WInternal Registers Subgroup: PCI Configuration HeaderByte Address: 06h - 07h The STATUS register i

vi AIC-6915 Ethernet LAN Controller Programmer’s ManualTransmit Buffer Descriptor Types 8-18Two Transmit Queues 8-20Transmit Producer-Consumer Model 8

7-8 AIC-6915 Ethernet LAN Controller Programmer’s Manual11 r/w 0STA: Signal Target Abort is set by the target of a PCI bus transaction if it is unable

7-9Register DescriptionsPCI DEVREVID (Device Revision ID) RegisterType: R Internal Registers Subgroup: PCI Configuration HeaderByte Address: 08hPCI Pr

7-10 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI Baseclass RegisterType: RInternal Registers Subgroup: PCI Configuration HeaderByte Addre

7-11Register DescriptionsPCI Hdrtype (Header Type) RegisterType: RInternal Registers Subgroup: PCI Configuration HeaderByte Address: 0EhBIST (Built-in

7-12 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI HighBASEADR0 (Base Address 0) RegisterType: R/WInternal Registers Subgroup: PCI Configura

7-13Register DescriptionsPCI SubSystemVendor ID RegisterType: RInternal Registers Subgroup: PCI Configuration HeaderByte Address: 2Ch - 2DhPCI SubSyst

7-14 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI CapPtr (Capabilities List Pointer) RegisterType: R/WInternal Registers Subgroup: PCI Conf

7-15Register DescriptionsPCI INTPINSEL (Interrupt Pin Select) RegisterType: RInternal Registers Subgroup: PCI Configuration HeaderByte Address: 3DhPCI

7-16 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCI MAXLAT (Maximum Latency) RegisterType: RInternal Registers Subgroup: PCI Configuration He

7-17Register DescriptionsPCI Functional Registers DefinitionThe following registers are accessible from PCI configuration, memory and direct I/O space

viiDocument Title: Document TitleStock Number: xxxxxx-xx Rev. x Page: Front Matter-viiPrint Spec Number: xxxxxx-xx Rev. xCurrent Date: 10/10/98 ECN Da

7-18 AIC-6915 Ethernet LAN Controller Programmer’s Manual18:16 r/w 000EpromCsWidth: Indicates the width of the EPROM chip-select. ‘000’ - 8 PCI cloc

7-19Register Descriptions6r/w0StopOnPerr: Specifies the behavior of the PCI master when a data parity error is encountered during an active DMA operat

7-20 AIC-6915 Ethernet LAN Controller Programmer’s ManualBacControl RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersByte Address

7-21Register DescriptionsPCIMonitor1 RegisterType: RInternal Registers Subgroup: PCI Functional RegistersByte Address: 48h - 4Bh1r/w0PREFERRXDMAREQ: C

7-22 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCIMonitor2 RegisterType: RInternal Registers Subgroup: PCI Functional RegistersByte Address:

7-23Register DescriptionsPMCSR (Power Management Control/Status) RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersByte Address: 5

7-24 AIC-6915 Ethernet LAN Controller Programmer’s ManualPME Event RegisterType: R/W Internal Registers Subgroup: Ethernet Functional RegistersByte Ad

7-25Register DescriptionsEEPROM Memory DefinitionTable 7-35. EEPROM Memory DefinitionByte Address Description/Function Value0 Vendor ID [7:0] 041 Vend

7-26 AIC-6915 Ethernet LAN Controller Programmer’s ManualPCIComplianceTesting RegisterType: R/WInternal Registers Subgroup: PCI Functional RegistersBy

7-27Register DescriptionsEthernet RegistersThe following registers are accessible from PCI configuration, memory, and direct I/O space. They are all s